In an output buffer circuit between LSIs, especially in a high-speed interface, it is necessary to design and manufacture a circuit to prevent or reduce dependency in output characteristics (especially in delay time) on fluctuation in power supply voltage. One of the main causes of variation in the output characteristics due to the fluctuation in power supply voltage is variation in output amplitude.
While a differential circuit employed in a bipolar semiconductor device is publicly known as an output buffer circuit for a high-speed interface, the problem remains that it is difficult to design the output buffer circuit as a CMOS circuit.
FIG. 3 is a circuitry diagram showing a conventional output buffer circuit employed in a high speed interface. The output buffer circuit includes an N-channel MOS transistor pair 208 and 209 as a differential pair having sources connected in common to one terminal of a current source (constant current source) 304 and gates connected to input terminals 506 and 507, respectively. The current source 304 has the other terminal for receiving a reference electric potential. The circuit further includes a current mirror circuit functioning as an active load for the differential pair, which current mirror circuit includes a P-channel MOS transistor 106 having a drain and a gate connected to a drain of the N-channel MOS transistor 209 and a source connected to a power supply, and a P-channel MOS transistor 105 having a drain connected to a drain of the N-channel MOS transistor 208, a gate connected to the gate of the P-channel MOS transistor 106, and a source connected to the power supply. The drain of the N-channel MOS transistor 208 is connected to an output terminal 508.
In the output buffer circuit, an amplitude of an output voltage at the output terminal 508 varies depending on fluctuation in power supply voltage, and the variation is wide.
There is a problem in that regulation of the output amplitude required for the high-speed interface is impossible in the prior output buffer circuit. The variation in output amplitude shifts signal transition timing (rise and fall time), thus causing difficulties in actualizing the high-speed interface.